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LT1910 Protected High Side MOSFET Driver
FEATURES
s s s s s s s
DESCRIPTIO
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8V to 48V Power Supply Range Protected from -15V to 60V Supply Transients Short-Circuit Protected Automatic Restart Timer Open-Collector Fault Flag Fully Enhances N-Channel MOSFET Switches Programmable Current Limit, Delay Time and Autorestart Period Voltage Limited Gate Drive Defaults to OFF State with Open Input Available in SO-8 Package
The LT(R)1910 is a high side gate driver that allows the use of low cost N-channel power MOSFETs for high side switching applications. It contains a completely self-contained charge pump to fully enhance an N-channel MOSFET switch with no external components. When the internal drain comparator senses that the switch current has exceeded the preset level, the switch is turned off and a fault flag is asserted. The switch remains off for a period of time set by an external timing capacitor and then automatically attempts to restart. If the fault still exists, this cycle repeats until the fault is removed, thus protecting the MOSFET. The fault flag becomes inactive once the switch restarts successfully. The LT1910 has been specifically designed for harsh operating environments such as industrial, avionics and automotive applications where poor supply regulation and/or transients may be present. The device will not sustain damage from supply transients of -15V to 60V. The LT1910 is available in the SO-8 package.
, LTC and LT are registered trademarks of Linear Technology Corporation.
APPLICATIO S
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Industrial Control Avionics Systems Automotive Switches Stepper Motor and DC Motor Control Electronic Circuit Breaker
TYPICAL APPLICATIO
5V 5.1k FAULT OUTPUT OFF ON
Fault Protected High Side Switch
24V LT1910 8 V+ FAULT 4 6 IN SENSE 2 5 TIMER GATE 3 GND 0.1F 1
0.50 0.45
Switch Drop vs Load Current
0.01 TOTAL DROP (V)
0.40 0.35 0.30 0.25 0.20 0.15 0.10
IRFZ34
+
10F 50V
LOAD
1910 TA01
0.05 0 0 1 3 2 LOAD CURRENT (A) 4 5
1910 TA02
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LT1910
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PACKAGE/ORDER INFORMATION
TOP VIEW GND 1 TIMER 2 FAULT 3 IN 4 8 7 6 5 V+ NC SENSE GATE
Supply Voltage (Pin 8) ............................... -15V to 60V Input Voltage (Pin 4) .................... (GND - 0.3V) to 15V GATE Voltage (Pin 5) .............................................. 75V SENSE Voltage (Pin 6) ....................................... V + 5V FAULT Voltage (Pin 3) ............................................ 36V Current (Pins 1, 2, 4, 5, 6, 8) ............................... 40mA Operating Ambient Temperature Range (Note 2) ...................................................-40C to 85C Junction Temperature Range ................ -40C to 125C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LT1910ES8 S8 PART MARKING 1910E
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 125C, JA = 150C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS +
SYMBOL IS IS(ON) VINH VINL IIN CIN VT(TH) VT(CL) IT VSENSE ISENSE VGATE - V+ PARAMETER Supply Current (OFF State) Delta Supply Current (ON State) Input High Voltage Input Low Voltage Input Current Input Capacitance (Note 3) Timer Threshold Voltage Timer Clamp Voltage Timer Charge Current Drain Sense Threshold Voltage Temperature Coefficient (Note 3) Drain Sense Input Current Gate Voltage Above Supply
The q denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C. V = 12V to 48V unless otherwise noted.
CONDITIONS V+ = 48V, VIN = 0.8V VIN = 2V, Measure Increase in IS
q q
MIN 1.2 2
TYP 1.9 0.8
MAX 2.5 1.2 0.8
UNITS mA mA V V A A pF V V A mV %/C A V V V V V V V s s s
VIN = 2V VIN = 5V VIN = 2V, Adjust VT VIN = 0.8V VIN = VT = 2V
q q
15 55 2.6 3.2 9 50
30 110 5 2.9 3.5 14 65 0.33 0.5 4.5 8.5 12 12 3.4 3.3 0.07 220 25 20
50 185 3.2 3.8 20 80 1.5 6 10 14 14 3.7 3.6 0.4 400 100 50
q
V+ = 48V, VSENSE = 65mV V+ = 8V V+ = 12V V+ = 24V V+ = 48V VIN = 2V, IF = 1mA, Adjust VT IF = 1mA V+ = 24V, VGATE = 32V, CGATE = 1nF V+ = 24V, VGATE = 2V, CGATE = 1nF V+ = 24V, (V+ - VSENSE)0.1V, CGATE = 1nF
q q q q
4 7 10 10 3.1 3.0 100
VF(TH) VFOL tON tOFF tOFF(CL)
FAULT Output High Threshold Voltage FAULT Output Low Threshold Voltage FAULT Output Low Voltage Turn-On Time Turn-Off Time Current Limit Turn-Off Time
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The LT1910E is guaranteed to meet performance specifications from 0C to 70C. Specifications over the - 40C to 85C operating temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Guaranteed but not tested.
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LT1910 TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
3.6 3.4 3.2 TA = 25C
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 0 10
ON STATE
3.5 3.0 2.5 2.0 1.5 1.0 0.5 OFF STATE ON STATE
INPUT VOLTAGE (V)
3.0
OFF STATE
30 40 20 SUPPLY VOLTAGE (V)
Input Current vs Temperature
200 180 TIMER THRESHOLD VOLTAGE (V) 160 INPUT CURRENT (A) 140 120 100 80 60 40 20 0 -50 -25 25 50 0 TEMPERATURE (C) 75 100
1910 G04
3.0 2.9 2.8 2.7 2.6 -50
TIMER CLAMP VOLTAGE (V)
VIN = 5V
VIN = 2V
MOSFET GATE VOLTAGE ABOVE V + (VGATE - V +) (V)
Timer Charge Current vs Temperature
20 TIMER CHARGE CURRENT (A) 18 16 14 12 10 8 -50 DRAIN SENSE THRESHOLD VOLTAGE (mV) VIN = VT = 2V 90 85 80 75 70 65 60 55 50 45
-25
0 25 50 TEMPERATURE (C)
UW
1910 G01
Supply Current vs Temperature
5.0 4.5 4.0 1.8 V + = 48V 2.0
Input Voltage vs Temperature
VINH 1.6 1.4 VINL 1.2 1.0 0.8 -50
50
0 -50
-25
25 50 0 TEMPERATURE (C)
75
100
1910 G02
-25
0 25 50 TEMPERATURE (C)
75
100
1910 G03
Timer Threshold Voltage vs Temperature
3.2 3.1 VIN = 2V 3.8 3.7 3.6 3.5 3.4 3.3
Timer Clamp Voltage vs Temperature
VIN 0.8V
-25
0 25 50 TEMPERATURE (C)
75
100
1910 G05
3.2 -50
-25
0 25 50 TEMPERATURE (C)
75
100
1910 G06
Drain Sense Threshold Voltage vs Temperature
V + = 24V
MOSFET Gate Voltage Above V+ (VGATE - V+) vs Supply Voltage
16 14 12 10 8 6 4 2 0 0 5 10 15 20 25 30 35 40 45 50 SUPPLY VOLTAGE (V)
LTC1266 * F04
TA = 25C
TA = 85C TA = -40C
75
100
1910 G07
40 -50
-25
25 50 0 TEMPERATURE (C)
75
100
1910 G08
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LT1910 TYPICAL PERFOR A CE CHARACTERISTICS
MOSFET Gate Drive Current vs VGATE - V+
100 TA = 25C
FAULT THRESHOLD VOLTAGE (V)
MOSFET GATE DRIVE CURRENT (A)
3.6 3.5
FAULT OUTPUT LOW VOLTAGE (V)
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1
V + = 8V
V + = 12V V + 24V
0.1 0 2 4 6 8 10 VGATE - V + (V) 12 14 16
Turn-On Time vs Temperature
400 V+ = 24V VGATE = 32V 350 CGATE = 1nF
TURN-OFF TIME (s)
AUTOMATIC RESTART PERIOD (ms)
TURN-ON TIME (s)
300 250 200 150 100 -50
-25
0 25 50 TEMPERATURE (C)
4
UW
1910 G10
Fault Threshold Voltage vs Temperature
3.7 VIN = 2V IF = 1mA 0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 3.1 -50 -25 0 25 50 TEMPERATURE (C) 75 100
1910 G11
Fault Output Low Voltage vs Temperature
IF = 1mA
FAULT HIGH THRESHOLD 3.4 3.3 FAULT LOW THRESHOLD 3.2
0 -50
-25
25 50 0 TEMPERATURE (C)
75
100
1910 G012
Turn-Off Time vs Temperature
100 V+ = 24V 90 VGATE = 2V CGATE = 1nF 80 70 60 50 40 30 20 10 CURRENT LIMIT NORMAL 1000
Automatic Restart Period vs Temperature
V + = 24V CT = 3.3F CT = 1F 100 CT = 0.33F
CT = 0.1F 10 -50 -30 -10 10 30 50 TEMPERATURE (C) 70 90
1910 G15
75
100
1910 G13
0 -50
-25
25 50 0 TEMPERATURE (C)
75
100
1910 G014
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LT1910
PI FU CTIO S
GND (Pin 1): Common ground. TIMER (Pin 2): A timing capacitor CT from the TIMER pin to ground sets the restart time following overcurrent detection. Upon detection of an overcurrent condition, CT is rapidly discharged to less than 1V and then recharged by a 14A nominal current source back to the 2.9V timer threshold, whereupon the restart is attempted. Whenever TIMER pulls below 2.9V, the GATE pin pulls low to turn off the external switch. This cycle repeats until the overcurrent condition goes away and the switch restarts successfully. During normal operation the pin clamps at 3.5V nominal. FAULT (Pin 3): The FAULT pin monitors the TIMER pin voltage and indicates the overcurrent condition. Whenever the TIMER pin is pulled below 3.3V at the onset of a current limit condition, the FAULT pin pulls active LOW. The FAULT pin resets HIGH immediately when the TIMER pin ramps above 3.4V during autorestart. The FAULT pin is an open-collector output, thus requiring an external pull-up resistor and is intended for logic interface. The resistor should be selected with a typical 1mA pull-up at low status and less than 2mA under worst-case conditions. IN (Pin 4): The IN pin threshold is TTL/CMOS compatible and has approximately 200mV of hysteresis. When the IN pin is pulled active HIGH above 2V, an internal charge pump is activated to pull up the GATE pin. The IN pin can be pulled as high as 15V regardless of whether the supply is on or off. If the IN pin is left open, an internal 75k pulldown resistor pulls the pin below 0.8V to ensure that the GATE pin is inactive LOW. GATE (Pin 5): The GATE pin drives the power MOSFET gate. When the IN pin is greater than 2V, the GATE pin is pumped approximately 12V above the supply. It has relatively high impedance (the equivalence of a few hundred k) when pumped above the rail. Care should be taken to minimize any loading by parasitic resistance to ground or supply. The GATE pin pulls LOW when the TIMER pin falls below 2.9V. SENSE (Pin 6): The SENSE pin connects to the input of a supply-referenced comparator with a 65mV nominal offset. When the SENSE pin is taken more than 65mV below supply, the MOSFET gate is driven LOW and the timing capacitor is discharged. The SENSE pin threshold has a 0.33%/C temperature coefficient (TC), which closely matches the TC of the drain sense resistor formed from the copper trace of the PCB. For loads requiring high inrush current, an RC timing delay can be added between the drain sense resistor and the SENSE pin to ensure that the current-sense comparator does not false trigger during start-up (see Applications Information). A maximum of 10k can be inserted between a drain sense resistor and the SENSE pin. If current sensing is not required, the SENSE pin is tied to supply. V+ (Pin 8): In addition to providing the operating current for the LT1910, the V+ pin also serves as the Kelvin connection for the current sense comparator. The V+ pin must be connected to the positive side of the drain sense resistor for proper current sensing operation.
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LT1910
BLOCK DIAGRA
V+ 14A
3.3V TIMER 2.9V
- - + -
1.4V 75k IN 75k 250
1910 BD
-
OPERATIO
(Refer to the Block Diagram)
The LT1910 GATE pin has two states, OFF and ON. In the OFF state it is held LOW, while in the ON state it is pumped to 12V above the supply by a self-contained 750kHz charge pump. The OFF state is activated when either the IN pin is below 0.8V or the TIMER pin is below 2.9V. Conversely, for the ON state to be activated, the IN pin must be above 2V and the TIMER pin must be above 2.9V. The IN pin has approximately 200mV of hysteresis. If it is left open, the IN pin is held LOW by a 75k resistor. Under normal conditions, the TIMER pin is held a diode drop above 2.9V by a 14A pull-up current source. Thus the TIMER pin automatically reverts the GATE pin to the ON state if the IN pin is above 2V. The SENSE pin normally connects to the drain of the power MOSFET, which returns through a low value drain sense resistor to supply. In order for the sense comparator to accurately sense the MOSFET drain current, the V+ pin must be connected directly to the positive side of the drain sense resistor. When the GATE pin is ON and the MOSFET
6
+
-
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FAULT V+
+ +
+ -
65mV
SENSE
GATE
1.4V OSCILLATOR AND CHARGE PUMP
+
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drain current exceeds the level required to generate a 65mV drop across the drain sense resistor, the sense comparator activates a pull-down NPN which rapidly pulls the TIMER pin below 2.9V. This in turn causes the timer comparator to override the IN pin and set the GATE pin to the OFF state, thus protecting the power MOSFET. When the TIMER pin is pulled below 3.3V, the fault comparator also activates the open-collector NPN to pull the FAULT pin LOW, indicating an overcurrent condition. When the MOSFET gate voltage is discharged to less than 1.4V, the TIMER pin is released. The 14A current source then slowly charges the timing capacitor back to 2.9V where the charge pump again starts to drive the GATE pin HIGH. If a fault condition still exists, the sense comparator threshold will again be exceeded and the timer cycle will repeat until the fault is removed. The FAULT pin becomes inactive HIGH if the TIMER pin charges up successfully above 3.4V (see Figure 1).
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LT1910
OPERATIO
APPLICATIO S I FOR ATIO
Input/Supply Sequencing
There are no input/supply sequencing requirements for the LT1910. The IN pin may be taken up to 15V with the supply at 0V. When the supply is turned on with the IN pin set HIGH, the MOSFET turn-on will be inhibited until the timing capacitor charges up to 2.9V (i.e., for one restart cycle). Isolating the Inputs Operation in harsh environments may require isolation to prevent ground transients from damaging control logic. The LT1910 easily interfaces to low cost optoisolators. The network shown in Figure 2 ensures that the input will be pulled above 2V, but not exceed the absolute maximum rating for supply voltages of 12V to 48V over the entire
12V TO 48V LOGIC INPUT 2k 100k
LT1910 4 LOGIC GROUND IN GND 1
1910 F02
51k
POWER GROUND
Figure 2. Isolating the Input
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OFF IN 0V V+ GATE 0V 3.5V 2.9V 0V 5V FAULT 0V
1910 F01
NORMAL
OVERCURRENT
NORMAL
12V
3.4V
TIMER
Figure 1. Timing Diagram
temperature range. The optoisolator must have less than 20A of dark current (leakage) at hot in order to maintain the OFF State (see Figure 2). Drain Sense Configuration The LT1910 uses supply referenced current sensing. One input of the current sense comparator is connected to a drain sense pin, while the second input is offset 65mV below the supply inside the device. For this reason, Pin 8 of the LT1910 must be treated not only as a supply pin, but also as the reference input for the current sense comparator. Figure 3 shows the proper drain sense configuration for the LT1910. Note that the SENSE pin goes to the drain end of the sense resistor, while the V+ pin is connected to the
24V 5V R1 5.1k 3 LT1910 8 V+ FAULT 6 4 IN SENSE 5 2 TIMER GATE GND 1 CT 1F RS 0.02 (PTC) Q1 IRFZ34 24V 2A SOLENOID
FAULT OUTPUT INPUT
+
C1 100F 50V
0V
1910 F03
Figure 3. Drain Sense Configuration
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LT1910
APPLICATIO S I FOR ATIO
supply at the same point as the positive end of the sense resistor. The drain sense threshold voltage has a positive temperature coefficient, allowing PTC sense resistors to be used (see Printed Circuit Board Shunts). The selection of RS should be based on the minimum threshold voltage: RS = 50mV/ISET Thus the 0.02 drain sense resistor in Figure 3 will yield a minimum trip current of 2.5A. This simple configuration is appropriate for resistive or inductive loads that do not generate large current transients at turn-on. Automatic Restart Period The timing capacitor CT shown in Figure 3 determines the length of time the power MOSFET is held off following a current limit trip. Curves are given in the Typical Performance Characteristics to show the restart period for various values of CT. For example, CT = 0.33F yields a 50ms restart period. Defeating Automatic Restart Some applications are required to remain off after a fault occurs. When the LT1910 is being driven from CMOS logic, this can be easily implemented by connecting resistor R2 between the IN and TIMER pins as shown in Figure 4. R2 supplies the sustaining current for an internal SCR which latches the TIMER pin LOW under a fault condition. The FAULT pin is set active LOW when the TIMER pin falls below 3.3V. This keeps the MOSFET gate from turning ON and the FAULT pin from resetting HIGH
5V R1 5.1k FAULT OUTPUT 5V ON = 5V CMOS LOGIC OFF = 0V R2 2k 3 4 2 FAULT IN LT1910 TIMER GND CT 1F 1
1910 F04
Figure 4. Latch-Off Configuration (Autorestart Defeated)
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until the IN pin has been recycled. CT is used to prevent the FAULT pin from glitching whenever the IN pin recycles to turn on the MOSFET unsuccessfully under an existing fault condition. Inductive vs Capacitive Loads Turning on an inductive load produces a relatively benign ramp in MOSFET current. However, when an inductive load is turned off, the current stored in the inductor needs somewhere to decay. A clamp diode connected directly across each inductive load normally serves this purpose. If a diode is not employed, the LT1910 clamps the MOSFET gate 0.7V below ground. This causes the MOSFET to resume conduction during the current decay with (V+ + VGS + 0.7V) across it, resulting in high dissipation peaks. Capacitive loads exhibit the opposite behavior. Any load that includes a decoupling capacitor will generate a current equal to CLOAD * (V/t) during capacitor in-rush. With large electrolytic capacitors, the resulting current spike can play havoc with the power supply and false trip the current sense comparator. Turn-on V/t is controlled by the addition of the simple network shown in Figure 5. This network takes advantage of the fact that the MOSFET acts as a source follower during turn-on. Thus the V/t on the source can be controlled by controlling the V/t on the gate.
CURRENT LIMIT DELAY NETWORK 8 6 RD (10k) LT1910 V/t CONTROL NETWORK 1N4148 GATE GND 1 C2 50F 50V 5 R1 100k R2 100k C1 Q1 IRFZ34 15V 1N4744 CLOAD
1910 F05
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24V
1N4148 CD
V+ SENSE
RS 0.01
+
+
Figure 5. Control and Current Limit Delay
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LT1910
APPLICATIO S I FOR ATIO
IPEAK = CLOAD * VG - VTH R1 * C1
The turn-on current spike into CLOAD is estimated by:
where VTH is the MOSFET gate threshold voltage. VG is obtained by plotting the equation: IGATE = VGATE R1
TRIP DELAY TIME (1 = RDCD)
on the graph of Gate Drive Current (IGATE) vs Gate Voltage (VGATE) as shown in Figure 6. The value of VGATE at the intersection of the curves for a given supply is VG. For example, if V+ = 24V and R1 = 100k, then VG = 18.3V. For VTH = 2V, C1 = 0.1F and CLOAD = 1000F, the estimated IPEAK = 1.6A. The diode and the second resistor in the network ensure fast current limit turn-off. When turning off a capacitive load, the source of the MOSFET can "hang up" if the load resistance does not discharge CLOAD as fast as the gate is being pulled down. If this is the case, a 15V zener may be added from gate to source to prevent VGS(MAX) from being exceeded.
800 700
GATE DRIVE CURRENT (A)
600 500 400 300 200 100 0 0
V + = 24V V + = 12V V + = 8V
V + = 48V IGATE = VGATE/105
10
40 30 GATE VOLTAGE (V)
20
50
60
1910 F06
Figure 6. Gate Drive Current vs Gate Voltage
Adding Current Limit Delay When capacitive loads are being switched or in very noisy environments, it is desirable to add delay in the drain current sense path to prevent false tripping (inductive loads normally do not need delay). This is accomplished by the current limit delay network shown in Figure 5. RD
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and CD delay the overcurrent trip for drain currents up to approximately 10 * ISET, above which the diode conducts and provides immediate turn-off (see Figure 7). To ensure proper operation of the timer, CD must be CT.
10 1 0.1 0.01 10 100 1 MOSFET DRAIN CURRENT (1 = SET CURRENT)
1910 F07
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Figure 7. Current Limit Delay Time
Printed Circuit Board Shunts The sheet resistance of 1oz copper clad is approximately 5 * 10 -4/square with a temperature coefficient of 0.39%/C. Since the LT1910 drain sense threshold has a similar temperature coefficient (0.33%/C), this offers the possibility of nearly zero TC current sensing using the "free" drain sense resistor made out of PC trace material. A conservative approach is to use 0.02" of width for each 1A of current for 1oz copper. Combining the LT1910 drain sense threshold with the 1oz copper resistance results in a simple expression for width and length: Width (1oz Cu) = 0.02" * ISET Length (1oz Cu) = 2" The width for 2oz copper would be halved while the length would remain the same. Bends may be incorporated into the resistor to reduce space; each bend is equivalent to approximately 0.6 * the width of a straight length. Kelvin connection should be employed by running a separate trace from the ends of the resistor back to the LT1910's V+ and SENSE pins. See Application Note 53 for further information on printed circuit board shunts.
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LT1910
APPLICATIO S I FOR ATIO
Low Voltage/Wide Supply Range Operation
When the supply is less than 12V, the LT1910's charge pump does not produce sufficient gate voltage to fully enhance the standard N-channel MOSFET. For these applications, a logic-level MOSFET can be used to extend the operating supply down to 8V. If the MOSFET has a maximum VGS rating of 15V or greater, then the LT1910 can also operate up to a supply voltage of 60V (absolute maximum rating of the V+ pin). Protecting Against Supply Transients The LT1910 is 100% tested and guaranteed to be safe from damage with 60V applied between the V+ and GND pins. However, when this voltage is exceeded, even for a few microseconds, the result can be catastrophic. For this reason it is imperative that the LT1910 is not exposed to supply transients above 60V. A transient suppressor, such as Diodes Inc.'s SMAJ48A, should be added between the V+ and GND pins for such applications. For proper current sense operation, the V+ pin is required to be connected to the positive side of the drain sense resistor (see Drain Sense Configuration). Therefore, the supply should be adequately decoupled at the node where the V+ pin and drain sense resistor meet. Several hundred microfarads may be required when operating with a high current switch. When the operating voltage approaches the 60V absolute maximum rating of the LT1910, local supply decoupling
5V R1 5.1k 3 8V TO 24V LT1910 8 V+ FAULT 6 4 IN SENSE 5 2 TIMER GATE GND 1
FAULT OUTPUT INPUT
CT 1F
Figure 8b. Low Side Driver for Source Current Sensing
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between the V+ and GND pins is highly recommended. An RC snubber with a transient suppressor are an absolute necessity. Note however that resistance should not be added in series with the V+ pin because it will cause an error in the current sense threshold. Low Side Driving Although the LT1910 is primarily targeted at high side (grounded load) switch applications, it can also be used for low side (supply connected load) switch applications. Figures 8a and 8b illustrate the LT1910 driving low side power MOSFETs. Because the LT1910 charge pump tries to pump the gate of the N-channel MOSFET above the supply, a clamp zener is required to prevent the VGS (absolute maximum) of the MOSFET from being exceeded.
12V TO 48V 5V R1 5.1k 3 4 V+ SENSE LT1910 8 6 RS 0.01 (PTC) 4A LOAD Q1 IRFZ44 15V 1N4744
1910 F08a
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FAULT OUTPUT INPUT
FAULT IN
+
5
C1 100F 100V
2
TIMER GATE GND CT 1F 1
0V
Figure 8a. Low Side Driver with Load Current Sensing
HV HV LOAD Q1 IRF630
51
15V 1N4744
+
2N2222 C1 10F 50V LT1006
+
-
RS 0.02
51
1910 F08b
LT1910
APPLICATIO S I FOR ATIO
The LT1910 gate drive is current limited for this purpose so that no resistance is needed between the GATE pin and zener. Current sensing for protecting low side drivers can be done in several ways. In the Figure 8a circuit, the supply voltage for the load is assumed to be within the supply operating range of the LT1910. This allows the load to be returned to supply through current sense resistor RS, providing normal operation of the LT1910 protection circuitry.
PACKAGE DESCRIPTIO
S8 Package 8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.189 - .197 (4.801 - 5.004) NOTE 3 8 7 6 5
.045 .005 .050 BSC
.245 MIN
.160 .005 .228 - .244 (5.791 - 6.197)
.030 .005 TYP RECOMMENDED SOLDER PAD LAYOUT .010 - .020 x 45 (0.254 - 0.508) .008 - .010 (0.203 - 0.254) 0- 8 TYP
.016 - .050 (0.406 - 1.270) NOTE: 1. DIMENSIONS IN
INCHES (MILLIMETERS) 2. DRAWING NOT TO SCALE 3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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If the load cannot be returned to supply through RS, or the load supply voltage is higher than the LT1910 supply, the current sense must be moved to the source of the low side MOSFET. Figure 8b shows an approach to source sensing. An operational amplifier (must common mode to ground) is used to level shift the voltage across RS up to the drain sense pin. This approach allows the use of a small sense resistor which could be made from PC trace material. The LT1910 restart timer functions the same as in the high side switch application.
.150 - .157 (3.810 - 3.988) NOTE 3 1 2 3 4 .053 - .069 (1.346 - 1.752) .004 - .010 (0.101 - 0.254) .014 - .019 (0.355 - 0.483) TYP .050 (1.270) BSC
SO8 0303
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LT1910
TYPICAL APPLICATIO
8V TO 24V OPERATING 32V TO 60V SHUTDOWN
Protected 1A Automotive Solenoid Driver with Overvoltage Shutdown
POWER GROUND
RELATED PARTS
PART NUMBER LTC 1153 LTC1155 LT1161 LTC1163 LTC1255 LTC1477 LTC1623 LTC1693 Family LTC1710 LTC4412
(R)
DESCRIPTION Autoreset Electronic Circuit Breaker Dual High Side Micropower MOSFET Driver Quad Protected High Side MOSFET Driver Triple 1.8V to 6V High Side MOSFET Driver Dual 24V High Side MOSFET Driver Protected Monolithic High Side Switch SMBus Dual High Side Switch Controller High Speed Single/Dual N-Channel/P-Channel MOSFET Drivers SMBus Dual Monolithic High Side Switch Low Loss PowerPath Controller
TM
PowerPath and ThinSOT are trademarks of Linear Technology Corporation.
12 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
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5V R1 5.1k 3 LT1910 8 V+ FAULT 6 4 IN SENSE 5 2 TIMER GATE GND 1 2N3904 R3 5.1k CT 1F RS 0.03 (PTC) Q1 MTD3055EL 24V 1A SOLENOID FAULT OUTPUT INPUT 30V 1N6011B R2 10k 1N4148
+
C1 10F 100V
1910 TA03
COMMENTS Programmable Trip Current, Fault Status Output Operates from 4.5V to 18V, 85A ON Current, Short-Circuit Protection 8V to 48V Supply Range, Individual Short-Circuit Protection 0.01A Standby Current, Triple Driver in SO-8 Package Operates from 9V to 24V, Short-Circuit Protection Low RDS(ON) 0.07 Switch, 2A Short-Circuit Protected 2-Wire SMBus Serial Interface, Built-In Gate Charge Pumps 1.5A Peak Output Current, 4.5V VCC 13.2V, SO-8 Package Two Low RDS(ON) 0.4/300mA Switches in 8-Lead MSOP Package Implements "Ideal Diode" Function, ThinSOTTM Package
sn1910 1910fs LT/TP 0403 2K * PRINTED IN USA
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(c) LINEAR TECHNOLOGY CORPORATION 2002

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